Nonvolatile memory device with load-supplying wired-or...

Details Nonvolatile memory device with load-supplying wired-or... Nonvolatile memory device with load-supplying wired-or...

2005-12-27

2009-06-30

Hur, J. H. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185250

Reexamination Certificate

active

07554850

ABSTRACT:
We describe a nonvolatile memory device with a wired-OR structure and method of driving the same that reduces peak current during the wired-OR operation. The nonvolatile semiconductor memory device includes a memory cell array including a plurality of bitlines and a plurality of memory cells to store data. A plurality of page buffers buffer main latch data responsive to the bitlines. An internal output line operates in an output drive voltage responsive to the main latch data. A global output line transfers a data bit responsive to the internal output line. An output switch circuit electrically connects the global output line to the internal output line during a wired-OR operation. And a data line control circuit charges the global output line with a charge current after discharging the same during the wired-OR operation.

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English language abstract of Korean Publication No. 2002-0087168.
English language abstract of Japanese Publication No. 11-203879.
English language abstract of Japanese Publication No. 2002-140899.

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