Memory with test mode output

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Details

Other Related Categories

C714S042000

Type

Reexamination Certificate

Status

active

Patent number

07610524

Description

ABSTRACT:
Methods of operating an apparatus allow a memory to generate a test mode signal to trigger a test, in response to the memory detecting a predetermined command from a system bus.

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