Semiconductor memory utilizing a method of coding data

Static information storage and retrieval – Addressing – Counting

Reexamination Certificate

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C365S189070, C365S239000

Reexamination Certificate

active

07551514

ABSTRACT:
A semiconductor memory device utilizing a data coding method in an initial operation. The device includes a plurality of counters that count the number of data bits and flag information data bits. A data coding unit selectively applies a first and second operation mode. The first operation mode codes the data of the first through nth data groups such that the counted number of data bits in a first logic state is minimized. The second operation mode codes the data of the first through nth data groups such that the difference between the number of data bits and flag information bits in the first and second logic state are minimized. This prevents the initial logic state of data from being changed due to a voltage drop in the initial operation of the device.

REFERENCES:
patent: 2003141877 (2003-05-01), None
patent: 1020020058423 (2002-07-01), None
patent: 1020030091233 (2003-12-01), None

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