Semiconductor memory and operation method for same

Details Semiconductor memory and operation method for same Semiconductor memory and operation method for same

2006-08-24

2009-06-16

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189090, C365S191000, C365S203000, C365S235000

Reexamination Certificate

active

07548468

ABSTRACT:
A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.

REFERENCES:
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patent: 6373783 (2002-04-01), Tomita
patent: 6667933 (2003-12-01), Tomita
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