Semiconductor memory device capable of high-speed cache read...

Details Semiconductor memory device capable of high-speed cache read... Semiconductor memory device capable of high-speed cache read...

2007-01-19

2009-12-22

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

Plural use of terminal

C365S185030

Reexamination Certificate

active

07636261

ABSTRACT:
Primary data caches are connected to a common signal line, and secondary data caches are connected to an I/O data line. While data in the secondary data cache is being output to the I/O data line, the common signal line is used to make determinations for data in flag cells. This increases the speed of a cache read operation.

REFERENCES:
patent: 6111787 (2000-08-01), Akaogi et al.
patent: 6137729 (2000-10-01), Choi
patent: 6178115 (2001-01-01), Shibata et al.
patent: 6185128 (2001-02-01), Chen et al.
patent: 6657891 (2003-12-01), Shibata et al.
patent: 2000-195280 (2000-07-01), None
patent: 2004-192789 (2004-07-01), None

Affiliated with

Also associated with

Rating

Semiconductor memory device capable of high-speed cache read... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device capable of high-speed cache read..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device capable of high-speed cache read... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4112183