Error correction code memory system with a small footprint...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

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07620875

ABSTRACT:
A method, apparatus and program storage device that provides an error correction code memory system with a small footprint and byte write operation. A memory controller virtualizes the memory controller interface, multiplexes ECC data onto the same pins as data, and stores replicated ECC data structures interleaved with data in system memory. These mechanisms enable a range of very cost effective small memory subsystems that support ECC operation in a minimum of standard commodity memory devices. ECC encoding is provided to support efficient byte write operations.

REFERENCES:
patent: 5961660 (1999-10-01), Capps et al.
patent: 7117421 (2006-10-01), Danilak
patent: 7152138 (2006-12-01), Spencer et al.
patent: 7242615 (2007-07-01), Nagashima
patent: 7464241 (2008-12-01), Vogt
patent: 7487428 (2009-02-01), Co et al.

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