Hybrid cryptographic accelerator and method of operation...

Details Hybrid cryptographic accelerator and method of operation... Hybrid cryptographic accelerator and method of operation...

2004-03-23

2009-06-02

Zand, Kambiz (Department: 2434)

Electrical computers and digital processing systems: support

Data processing protection using cryptography

C713S002000, C713S002000

Reexamination Certificate

active

07543158

ABSTRACT:
For use in a system-on-a-chip (SoC) having a secure execution environment (SEE) containing secure memory, a cryptographic accelerator, a method of performing cryptography therewith and an SoC incorporating the cryptographic accelerator or the method. In one embodiment, the cryptographic accelerator includes: (1) a key register located within the SEE and coupled to the secure memory to receive a cryptographic key therefrom and (2) data input and output registers located outside of the SEE and coupled to the key register to allow the cryptographic key to be applied to input data arriving via the data input register to yield output data via the data output register.

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