Prevention of conflicting cache hits without an attendant...

Details Prevention of conflicting cache hits without an attendant... Prevention of conflicting cache hits without an attendant...

2003-06-20

2009-02-17

Ellis, Kevin L (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S130000, C712S203000

Reexamination Certificate

active

07493448

ABSTRACT:
A multiprocessor system includes a plurality of processors that share a multiple-way set-associative cache memory that includes a directory and a data array, the multiprocessor system being partitioned such that the plurality of processor operate as independent systems. The multiprocessor system also includes a hit judgement circuit that determines hits of, of the ways in the sets that are designated at the time a processor of a particular partition accesses the shared cache memory, only those ways that have been allocated in advance in accordance with active signals that are supplied as output at the time of the access.

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