Flash EEPROM having memory cell arrays supplied respectively wit

Details Flash EEPROM having memory cell arrays supplied respectively wit Flash EEPROM having memory cell arrays supplied respectively wit

1994-01-07

1995-09-12

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365185, 365218, 365900, 371 102, G11C 1140

Patent

active

054503604

ABSTRACT:
Disclosed herein is a flash type EEPROM which includes a first memory cell array having a plurality of first memory cells, a second memory array having a plurality of memory cells which are smaller in number than the first memory cells, a voltage generator operatively generating an erasing voltage in an erase operation mode, a first transfer gate circuit operatively transferring the erasing voltage to each of the first and a second transfer gate circuit operatively transferring the erasing voltage to each of the second memory cells, the first transfer gate circuit having a current driving capability larger than the current driving capability of the second transfer gate circuit.

REFERENCES:
patent: 4648074 (1987-03-01), Pollachek
patent: 4884241 (1989-11-01), Tanaka et al.
patent: 5243570 (1993-09-01), Saruwatari

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