Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-21
2009-12-15
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07634743
ABSTRACT:
Method for updating a circuit design. A modification to a netlist that includes original components and original spare cells is received. Original components that are not required by the modification are identified, disconnected and marked or made new spare cells. A pool of spare cells is generated and includes original and new spare cells. The netlist is updated by adding new components, and added components are mapped to spare cells selected from the pool. If mapping does not satisfy a design constraint, such as a timing constraint, then original components can be de-mapped and made spare cells, added components are mapped to spare cells resulting from de-mapping, and de-mapped components can be re-mapped to other spare cells.
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Cadence Design Systems Inc.
Chiang Jack
Parihar Suchin
Vista IP Law Group LLP
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