Method of making multi-chip electronic package with reduced...

Details Method of making multi-chip electronic package with reduced... Method of making multi-chip electronic package with reduced...

2007-12-21

2009-11-24

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C257SE21477, C257SE21506, C438S667000

Reexamination Certificate

active

07622384

ABSTRACT:
A method of making an electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. The method involves forming the line patterns in such a manner so as to reduce line skew.

REFERENCES:
patent: 4159915 (1979-07-01), Anantha et al.
patent: 4879631 (1989-11-01), Johnson et al.
patent: 4882454 (1989-11-01), Peterson et al.
patent: 4992850 (1991-02-01), Corbett et al.
patent: 5026624 (1991-06-01), Day et al.
patent: 5072075 (1991-12-01), Lee et al.
patent: 5121190 (1992-06-01), Hsiao et al.
patent: 5300402 (1994-04-01), Card, Jr. et al.
patent: 5483421 (1996-01-01), Gedney et al.
patent: 5574630 (1996-11-01), Kresge et al.
patent: 5615087 (1997-03-01), Wieloch
patent: 5661089 (1997-08-01), Wilson
patent: 5798563 (1998-08-01), Feilchenfeld et al.
patent: 5838063 (1998-11-01), Sylvester
patent: 5849610 (1998-12-01), Zhu
patent: 5894173 (1999-04-01), Jacobs et al.
patent: 5900675 (1999-05-01), Appelt et al.
patent: 5926377 (1999-07-01), Nakao et al.
patent: 5982630 (1999-11-01), Bhatia
patent: 6161215 (2000-12-01), Hollenbeck et al.
patent: 6246010 (2001-06-01), Zenner et al.
patent: 6351393 (2002-02-01), Kresge et al.
patent: 6442057 (2002-08-01), Song et al.
patent: 6683503 (2004-01-01), Mizuno et al.
patent: 6836163 (2004-12-01), Spehar
patent: 7332818 (2008-02-01), Memis
patent: 2004/0053483 (2004-03-01), Nair et al.
patent: 11-087560 (1999-03-01), None
patent: 2000-022071 (2000-01-01), None
patent: 2000-024150 (2000-01-01), None
IBM TDB, “Multi Chip Cooling Plate”, Jul. 1978, pp. 745-746.
IBM TDB, “Simultaneous Chip Placement—Multi-Chip Modules”, Feb. 1982, pp. 4647-4649.
IBM TDB, “High Performance Multi-Chip Module”, Nov. 1987, pp. 437-439.
IBM TDB, “Low-Cost, High-Power, Multi-Chip Module Design”, Aug. 1988, pp. 451-452.
IBM TDB, “Thermally Conductive Substrate Mounted Multi-Chip Module Cap”, Sep. 1993, pp. 623-624.

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