Electrical computers and digital processing systems: processing – Instruction fetching – Of multiple instructions simultaneously
Reexamination Certificate
2005-10-17
2009-06-23
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Instruction fetching
Of multiple instructions simultaneously
C712S238000, C712S239000, C712S240000
Reexamination Certificate
active
07552314
ABSTRACT:
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction for a “block” of instruction memory. The block of instruction memory is represented by a block entry in the fetch-block branch target buffer. The block entry represents one recorded control-transfer instruction (such as a branch instruction) and a set of sequentially preceding instructions, up to a fixed maximum length N. Indexing into the fetch-block branch target buffer yields an answer whether the block entry represents memory that contains a previously executed a control-transfer instruction, a length value representing the amount of memory that contains the instructions represented by the block, and an indicator for the type of control-transfer instruction that terminates the block, its target and outcome. Both the decode and execution pipelines include correction capabilities for modifying the block branch target buffer dependent on the results of the instruction decode and execution and can include a mechanism to correct malformed instructions.
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David A. Patterson et al., “Computer Architecture A Quantitative Approach”, 1996, pp. 262-271.
Gelman Anatoly
Schnapp Russell
Jorgenson Lisa K.
Kim Kenneth S
Munck William A.
STMicroelectronics Inc.
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