Structure and method for fabricating self-aligned metal...

Details Structure and method for fabricating self-aligned metal... Structure and method for fabricating self-aligned metal...

2007-10-26

2009-11-10

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S412000, C257S369000

Reexamination Certificate

active

07615831

ABSTRACT:
A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.

REFERENCES:
patent: 5670812 (1997-09-01), Adler et al.
patent: 5675185 (1997-10-01), Chen et al.
patent: 5744384 (1998-04-01), Adler et al.
patent: 5757050 (1998-05-01), Adler et al.
patent: 6022766 (2000-02-01), Chen et al.
patent: 6713791 (2004-03-01), Hsu et al.
patent: 6908850 (2005-06-01), Doris et al.
patent: 6930030 (2005-08-01), Rausch et al.
patent: 6939751 (2005-09-01), Zhu et al.
patent: 7098536 (2006-08-01), Yang et al.
patent: 7105440 (2006-09-01), Luo et al.
patent: 7135724 (2006-11-01), Chen et al.
patent: 2002/0100918 (2002-08-01), Hsu et al.
patent: 2004/0248348 (2004-12-01), Rausch et al.
patent: 2005/0054169 (2005-03-01), Wagner et al.
patent: 2005/0055494 (2005-03-01), Doris et al.
patent: 2005/0090066 (2005-04-01), Zhu et al.
patent: 2005/0093030 (2005-05-01), Doris et al.
patent: 2005/0158937 (2005-07-01), Yang et al.
patent: 2005/0263825 (2005-12-01), Frohberg et al.
patent: 2006/0065914 (2006-03-01), Chen et al.
patent: 2006/0091471 (2006-05-01), Frohberg et al.
patent: 2006/0099793 (2006-05-01), Yang et al.
patent: 2006/0148215 (2006-07-01), Zhu et al.
patent: 2006/0154413 (2006-07-01), Luo et al.
patent: 2006/0163670 (2006-07-01), Ellis-Monaghan et al.
patent: 2006/0172500 (2006-08-01), Yang et al.
patent: 2006/0199326 (2006-09-01), Zhu et al.
patent: 2006/0261477 (2006-11-01), Yang et al.
patent: 2006/0292779 (2006-12-01), Chen et al.
patent: 2007/0018202 (2007-01-01), Zhu
patent: 2007/0018252 (2007-01-01), Zhu
patent: 2008/0169510 (2008-07-01), Kumar et al.
patent: 2009/0017625 (2009-01-01), Lee et al.
Pan, J., et al., “Novel Approach to Reduce Source/drain Series Resistance in High Performance CMOS Devices Using Self-Aligned CoWP Process for 45 nm Node UTSOI Transistors with 20 nm Gate Length”, VLSI 2006.

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