Method of manufacturing an insulaed gate transistor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

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438164, 438564, H01L 2100, H01L 2184, H01L 2122, H01L 2138

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active

059131110

ABSTRACT:
This invention provides a transistor manufacture method comprising the steps of forming, on a semiconductor substrate, an insulating film being made open at least in an introducing portion through which an impurity for forming a drain region other than a lightly-doped region is introduced, then forming a gate electrode and a drain electrode each containing an impurity, and then introducing the impurity through between the gate electrode and the drain electrode to thereby form the lightly-doped region; and introducing the impurity from the drain electrode through the impurity introducing portion with heat treatment, to thereby form the drain region. A transistor manufactured by the above method is also provided.

REFERENCES:
patent: 3887993 (1975-06-01), Okada et al.
patent: 4069067 (1978-01-01), Ichinoe
patent: 4072545 (1978-02-01), De La Moneda
patent: 4341009 (1982-07-01), Bartholomew et al.
patent: 4536943 (1985-08-01), Kakumu
patent: 4731318 (1988-03-01), Roche et al.
patent: 4945070 (1990-07-01), Hsu
patent: 4992389 (1991-02-01), Ogura et al.
patent: 5031010 (1991-07-01), Mikata et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5200639 (1993-04-01), Ishizuka et al.
patent: 5312518 (1994-05-01), Kadumura
patent: 5389557 (1995-02-01), Jung-Suk
patent: 5700700 (1997-12-01), Hwang
patent: 5733803 (1998-03-01), Mueller
T. Hosoya, "A Self-Aligning Contact Process For MOS LSI", IEEE Transactions on Electron Devices, vol. ED-28, No. 1, Jan. 1981, pp. 77-82.
P. Ko, "SiGMOS-A Silicon Gigabit/S NMOS Technology", Int'l Electron Devices Meeting 1983, Tech. Dig., Washington DC, Dec. 5-7, 1983, pp. 751-753.

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