Semiconductor wafer, semiconductor chip and dicing method of...

Details Semiconductor wafer, semiconductor chip and dicing method of... Semiconductor wafer, semiconductor chip and dicing method of...

2008-07-25

2009-12-29

Lee, Calvin (Department: 2892)

Semiconductor device manufacturing: process

Semiconductor substrate dicing

Having specified scribe region structure

Reexamination Certificate

active

07638411

ABSTRACT:
The metal wirings of the uppermost layer are exposed so as to be contactable to the probe and arranged so as to be spatially separated from one another via spaces that are approximately parallel to the longitudinal direction of the dicing area, and the position and size of the space is designed considering a thickness of a cutting edge of a blade and relative positioning error, and the blade does not cross any metal wirings when the blade passes through the dicing area, thereby preventing the generation of an abruption or a burr due to the dicing to enhance a yield in IC production.

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Japanese Office Action issued in Japanese Patent Application No. JP 2002-302993, dated Dec. 24, 2008.

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