Method of and circuit for interleaving data in a data coder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S702000, C714S755000

Reexamination Certificate

active

07552377

ABSTRACT:
According to one aspect of the invention, a method of interleaving data for enabling data coding in a communication network is disclosed, the method including storing parameters required to output address sequences for a matrix, receiving a block size associated with a block of data at a circuit for interleaving data, outputting parameters associated with the stored parameters based upon the block size, and producing an address sequence using the parameters. A circuit for interleaving data for data coding in a communication network is also disclosed. The circuit includes a lookup table storing parameters required to output address sequences for a matrix. A search coupled to the lookup table receives a clock size associated with a matrix and outputs parameters based upon the block size. A computation circuit coupled to receive the parameters outputs an address sequence using the parameters.

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Xilinx, Inc.; “3GPP Turbo Encoder” DS319, Product Specification, Nov. 11, 2004, pp. 1-14, available from Xilinx, Inc., 2100 Logic Drive, San Jose, 95124.
3rdGeneration Partnership Project; Technical Specification Group Radio Access Network; Multiplexing and channel coding (FDD), 3G TS 25.212 v3.20 (Mar. 2000), Release 1999, http://www.3gpp.org, 3GPP, 650 Route des Lucioles, Sophia Antipolis, Valbonne France.

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