Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-06-02
2009-02-03
Le, Don P (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S026000
Reexamination Certificate
active
07486104
ABSTRACT:
An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.
REFERENCES:
patent: 5467455 (1995-11-01), Gay et al.
patent: 5553250 (1996-09-01), Miyagawa et al.
patent: 5663661 (1997-09-01), Dillon et al.
patent: 5666078 (1997-09-01), Lamphier
patent: 5982191 (1999-11-01), Starr
patent: 5995894 (1999-11-01), Wendte
patent: 6060907 (2000-05-01), Vishwanthaiah
patent: 6157206 (2000-12-01), Taylor
patent: 6232792 (2001-05-01), Starr
patent: 6308232 (2001-10-01), Gasbarro
patent: 6356105 (2002-03-01), Volk
patent: 6356106 (2002-03-01), Greeff et al.
patent: 6424200 (2002-07-01), McNitt et al.
patent: 6762620 (2004-07-01), Jang et al.
patent: 6781405 (2004-08-01), Rajan et al.
patent: 6856169 (2005-02-01), Frans et al.
patent: 6894691 (2005-05-01), Juenger
patent: 6924660 (2005-08-01), Nguyen et al.
patent: 6965529 (2005-11-01), Zumkehr
patent: 6980020 (2005-12-01), Best et al.
patent: 7123047 (2006-10-01), Lim
patent: 7148721 (2006-12-01), Park
patent: 2003/0012046 (2003-01-01), Lee et al.
patent: 2003/0039151 (2003-02-01), Matsui
patent: 2004/0201402 (2004-10-01), Rajan et al.
patent: 2005/0226080 (2005-10-01), Lee
patent: 2006/0007761 (2006-01-01), Ware et al.
patent: 2006/0071683 (2006-04-01), Best et al.
patent: 2006/0077731 (2006-04-01), Ware et al.
patent: 2007/0007992 (2007-01-01), Bains
patent: 2007/0070717 (2007-03-01), Kim
patent: 102005036528 (2007-02-01), None
patent: 2005/119471 (2005-12-01), None
patent: WO 97/02658 (1997-01-01), None
patent: WO 98/04041 (1998-01-01), None
patent: WO 00/41300 (2000-07-01), None
patent: WO 00/70474 (2000-11-01), None
patent: WO 2004/061690 (2004-07-01), None
patent: WO2007/078496 (2007-08-01), None
Nanya Technology Corp., “512Mb DDR2 SDRAM,” Preliminary Specification, Nanya Technology Corp. Dec. 18, 2003, Rev. 0.2, 80 pages.
Samsung Electronics Corp., Inc., “GDDR2 ODT On/Off Control Method (Single Rank / Dual Rank)” Application Note, Samsung Product Planning & Application Eng. Team, Jul. 2003 (Revision 0.0) 12 pages.
Farrell, Todd, “Core Architecture Doubles MEM Data Rate,” in Electronic Engineering Times Asia, Dec. 16, 2005. 4 pages.
Micron Technical Note, TN-47-07: DDR2 Simulation Support; Rev A Jul. 2005.
DDR2 ODT Control; Product Planning & Application Engineering Team, Dec. 2004, pp. 8.
512M bits DDR3 SDRAM, Prelimnary Data Sheet, Elpida Memory, Inc. 2005-2006, Document No. E0785E11 (Ver. 1.1), Feb. 2006, 4 pages, www.elpida.com.
Chris Johnson, “Graphics DDR3 On-Die Termination and Thermal Considerations,” Designline, vol. 12, Issue 1, Micron, 8 pages, 2003.
Chris Johnson, “The Future of Memory: Graphics DDR3 SDRAM Functionality,” Designline, vol. 11, Issue 4, Micron, 8 pages, 2002.
D.Y. Lee and Desi Rhoden, “DDR/DDR2/DDR3 Tutorial,” Samsung and Inphi, JEDEX San Jose, © 2005, 130 pages.
Desi Roden, Inphi Corp., “The Evolution of DDR,” Via Technology Forum 2005, 23 pages. drhoden@inphi-corp.com.
Dr. William Wu Shen, Infineon Technologies, “DDR3 Functional Outlook,” JEDEX San Jose, Apr. 2006, 31 pages.
Dr. William Wu Shen, Infineon Technologies, “System Challenges on DDR3 High Speed Clock/Address/Command Fly-by Bus Technology,” JEDEX San Jose, Apr. 2006, 27 pages.
DRAM Module Market Overview, SimpleTech, Bill Gervasi, JEDEX Shanghai, Oct. 25-26, 2005, 50 pages.
Farrell, Todd, “Core architecture doubles mem data rate,” Micron Technology, Inc., Dec. 16, 2005, 4 pages. http://www.eetasia.com/ARTICLES/2005DEC/B/EEOL—2005DEC16—STOR—TA.pdf.
Hans-Peter Trost, Press Presentation DDR3 Introduction, Memory Products Group, Infineon Technologies AG, Jun. 2005, 11 pages.
Hynix and DDR3, Keynote Address at JEDEX Shanghai 2005, Oct. 2005, 24 pages.
Jeff Janzen, “DDR2 Offers New Features and Functionality,” Designline, vol. 12, Issue 2, Micron, 16 pages, 2003.
K.H. Lee, MultimediaCard Solutions of Digital Storage Applications, Samsung Electronics, JEDEX Shanghai, Oct. 25-26, 2005, 28 pages.
Micron Technical Note, “DDR2-533 Memory Design Guide for Two-DIMM Unbuffered Systems,” TN-47-01, 2003, 19 pages.
Rainer Weidlich, “What comes next in commodity DRAMS—DDR3,” Infineon Technologies, Jun. 2005, 4 pages.
Samsung, 512Mb E-die DDR3 SDRAM Specification, Preliminary Specification, Rev. 0.5, Dec. 2006, 55 pages.
Shen, William, “DDR3 Functional Outlook,” Infineon, JEDEX Shanghai, Oct. 25-26, 2005, 30 pages.
International Search Report and the Written Opinion of the International Searching Authority for International Application RBS2.P057WO, European Patent Office, Apr. 7, 2008, 16 pages.
Invitation to Pay Additional Fees and Communicatuion Relating to the Results of the Partial International Search in International Application PCT/US2007/069471, European Patent Office, Jan. 16, 2008, 5 pages.
JEDEC Standard, DDR2 SDRAM Specification, JESD79-2B (Revision of JESD79-2A), JEDEC Solid State Technology Association, Jan. 2005, 7 pages.
Oh Kyung Suk
Shaeffer Ian P.
Le Don P
RAMBUS Inc.
Shemwell Mahamedi LLP
LandOfFree
Integrated circuit with graduated on-die termination does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit with graduated on-die termination, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit with graduated on-die termination will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4096583