Memory correction system and method

Details Memory correction system and method Memory correction system and method

2007-11-02

2009-10-06

Luu, Pho M (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000

Reexamination Certificate

active

07599235

ABSTRACT:
An error correction system and method operable to identify and correct a memory module disposed within a computer memory system. In one embodiment, the memory system comprises a first memory module and a second memory module, each comprising a plurality of memory devices; and a memory controller operably coupled to the first memory module and the second memory module, the memory controller operable to use an error correction code (ECC) word, comprising data and redundant data, to detect module-level errors in the first and second memory modules.

REFERENCES:
patent: 7096406 (2006-08-01), Kanazawa et al.
patent: 7307902 (2007-12-01), Thayer

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