Transistors fabricated using a reduced cost CMOS process

Details Transistors fabricated using a reduced cost CMOS process Transistors fabricated using a reduced cost CMOS process

2007-08-02

2009-08-11

Menz, Douglas M (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S306000, C257SE29256

Reexamination Certificate

active

07573098

ABSTRACT:
An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped source and drain regions of the second conductivity type formed in the semiconductor substrate and being self-aligned to the edges of the dielectric spacers. The first and second well regions extend from the respective heavily doped regions through an area under the spacers to the third well region. The first and second well regions bridge the source and drain regions to the channel region of the transistor formed by the third well.

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