Method to reduce power in active shield circuits that use...

Electronic digital logic circuitry – Security

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C340S500000

Reexamination Certificate

active

07622944

ABSTRACT:
The present invention provides a method and apparatus for securing an integrated circuit. A pair of conductive security traces are arranged on an integrated circuit. Driver means provide complementary HIGH and LOW voltage levels to a respective first end of each of the conductive security traces. A first switch means temporarily interrupts the driver means and isolates the pair of conductive security traces. A second switch means temporarily connects the first ends of the isolated pair of conductive security traces to each other so that both conductive traces are at the same voltage. The voltage at the first end of one of the security traces at the LOW voltage is then boosted to one-half of the HIGH voltage level (VDD/2) by the HIGH (VDD) voltage level at the first end of the other security trace. First and second comparators are provided, each of which compares voltages on their respective first ends of the pair of conductive security traces with voltages on a respective second end of the pair of conductive security traces. Means are provided for logically combining the output signals of the first and second comparators.

REFERENCES:
patent: 4593384 (1986-06-01), Kleijne
patent: 4684931 (1987-08-01), Parks
patent: 4691350 (1987-09-01), Kleijne et al.
patent: 4807284 (1989-02-01), Kleijne
patent: 5406630 (1995-04-01), Piosenka et al.
patent: 5420379 (1995-05-01), Zank et al.
patent: 5635862 (1997-06-01), Abramson et al.
patent: 5642061 (1997-06-01), Gorney
patent: 5675319 (1997-10-01), Rivenberg et al.
patent: 6246970 (2001-06-01), Silverbrook et al.
patent: 6396400 (2002-05-01), Epstein et al.
patent: 6646565 (2003-11-01), Fu et al.
patent: 6774790 (2004-08-01), Houston
patent: 7352203 (2008-04-01), Ziomek
patent: 2003/0042970 (2003-03-01), Humphrey
patent: 2004/0032304 (2004-02-01), Anthony et al.
patent: 2004/0268136 (2004-12-01), Mitsuishi
patent: 2005/0223152 (2005-10-01), Sugaware
patent: 2006/0250239 (2006-11-01), Melton
patent: 2007/0040256 (2007-02-01), Tuyls et al.
patent: WO-2008082989 (2008-07-01), None
“U.S. Appl. No. 11/616,102, Notice of Allowance mailed Jan. 9, 2008”, 6 pgs.
“International Application Serial No. PCT/US2007/88139, International Search Report mailed May 1, 2008”, 3 pgs.
“International Application Serial No. PCT/US2007/88139, International Written Opinion mailed May 1, 2008”, 6 pgs.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method to reduce power in active shield circuits that use... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method to reduce power in active shield circuits that use..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method to reduce power in active shield circuits that use... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4088952

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.