Memory circuit, such as a DRAM, comprising an error...

Details Memory circuit, such as a DRAM, comprising an error... Memory circuit, such as a DRAM, comprising an error...

2005-12-13

2009-06-16

Chaudry, Mujtaba K (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S718000

Reexamination Certificate

active

07549109

ABSTRACT:
A dual port memory circuit has a memory plane including first and second modules each constituted of an array of memory cells arranged in columns and rows, each row of the memory plane allowing storage of a page of words, each word of the page being identified by an address organized according to a hierarchical division defined by (@MSB, row address, column address), with @MSB identifying a particular module among the n modules. The circuit comprises first and second address buses, and first and second data buses used for reading and writing the modules, respectively. For each memory module, there is provided a multiplexer having two inputs connected to both address buses. The multiplexer output is connected to a row decoder and to first and second column decoders corresponding to the first and second data buses. Each multiplexer is controlled to allow writing and simultaneous reading of two distinct modules.

REFERENCES:
patent: 4969148 (1990-11-01), Nadeau-Dostie et al.
patent: 5117393 (1992-05-01), Miyazawa et al.
patent: 5293347 (1994-03-01), Ogawa
patent: 5680365 (1997-10-01), Blankenship
patent: 5751638 (1998-05-01), Mick et al.
patent: 5798656 (1998-08-01), Kean
patent: 5831448 (1998-11-01), Kean
patent: 6018817 (2000-01-01), Chen et al.
patent: 6631441 (2003-10-01), Harrand et al.
patent: 6675256 (2004-01-01), Harrand et al.
patent: 6701482 (2004-03-01), Salvi et al.
patent: 6874111 (2005-03-01), Adams et al.
patent: 7076714 (2006-07-01), Cook et al.
patent: 7127668 (2006-10-01), McBryde et al.
patent: 2002/0162069 (2002-10-01), Laurent
patent: 2003/0204795 (2003-10-01), Adams et al.
patent: 2004/0264279 (2004-12-01), Wordeman et al.
patent: 2005/0185492 (2005-08-01), Harrand
patent: 0 306 726 (1989-03-01), None
patent: 2 289 779 (1995-11-01), None
patent: 55-55499 (1980-04-01), None
Chang, T-S., et al., “Embedded Memory Module Design for Video Signal Processing,” inProceedings of the Signal Processing Society Workshop on VLSI Signal Processing VIII, Sakai, Japan,, Sep. 16-18, 1995, pp. 501-510.

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