Method for the generation of static noise check data in the...

Details Method for the generation of static noise check data in the... Method for the generation of static noise check data in the...

2005-03-29

2009-02-17

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07493579

ABSTRACT:
In the static noise check of the LSI hierarchical design, in order to reduce the data volume of the common parts and load of the design operation and design automation, when a plurality of cores, comprising same sub-chips, are present, the static noise check data for the whole chip is generated from the core-level design data of one of the cores, and the chip-level design data.

REFERENCES:
patent: 5519630 (1996-05-01), Nishiyama et al.
patent: 7325212 (2008-01-01), Ishikawa
patent: 05-216950 (1993-08-01), None
patent: 11-218900 (1999-08-01), None
“Analysis of Static Crosstalk Delay and IR Drop Delay,” Nihon Synopsis Co., Ltd., Sep. 2002.

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