Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2004-09-01
2009-10-20
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S058000, C710S061000, C710S105000, C710S106000, C709S230000
Reexamination Certificate
active
07606955
ABSTRACT:
A master/slave system architecture that includes a single wire bus, a master device and bus interface coupled to the bus. The system further includes plurality of slave devices having respective bus interfaces coupled to the bus. Each of the slave devices having a designated device identification. There is further provided a communication protocol implemented over the single wire bus and employed by the master and the slave devices. The protocol includes bus transactions composed each of bit signals that belong each to a bit signal type from among a plurality of bit signal types. Each bit signal type has a time interval that is discernible from respective time intervals of all other bit signal types from among the plurality of bit signal types.
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Falik Ohad
Flachs Victor
Dang Khanh
National Semiconductor Corporation
Zaman Faisal M
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