Low latency coherency protocol for a multi-chip...

Details Low latency coherency protocol for a multi-chip... Low latency coherency protocol for a multi-chip...

2004-10-08

2009-08-18

Peugh, Brian R (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S146000, C711S133000

Reexamination Certificate

active

07577794

ABSTRACT:
Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.

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