Memory device and method of operating such a memory device

Details Memory device and method of operating such a memory device Memory device and method of operating such a memory device

2007-11-01

2009-11-03

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S189011, C365S189110, C365S185250, C365S185180, C365S226000

Reexamination Certificate

active

07613052

ABSTRACT:
A memory device and method of operation is provided, the memory device having a plurality of memory cells arranged in at least one column, with each column having at least one bit line and a supply voltage line associated therewith. A capacitance exists between the supply voltage line and associated at least one bit line for each column. Control circuitry is used to control, for each column, connection of a voltage source to the associated supply voltage line. For a predetermined period during a memory access operation, the control circuitry disconnects the supply voltage line for at least the selected column from the voltage source, such that a voltage level on that supply voltage line changes in response to any change in voltage on the associated at least one bit line. This basic mechanism can be used to provide a variety of assist mechanisms, such as a write assist mechanism, a bit flip assist mechanism and a read assist mechanism. The technique of the present invention provides a particularly simple and power efficient technique for providing such assist mechanisms.

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H. Pilo et al, “An SRAM Design in 65nm and 45nm Technology Nodes Featuring Read and Write-Assist Circuits to Expand Operating Voltage” 2006 Symposium on VLSI Circuits Digest of Technical Papers.
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