System and method for reducing store latency

Details System and method for reducing store latency System and method for reducing store latency

2005-12-19

2009-10-20

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S154000, C711S156000, C711S207000

Reexamination Certificate

active

07606981

ABSTRACT:
According to one embodiment of the invention, a method comprises verifying that a cache block is not exclusively owned, and if not, transmitting a message identifying both the cache block and a caching agent requesting ownership of the cache block to a broadcast interconnect.

REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6868485 (2005-03-01), Conway
patent: 7096323 (2006-08-01), Conway et al.
patent: 7373466 (2008-05-01), Conway
patent: 2005/0055502 (2005-03-01), Hass et al.

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