Method for register allocation during instruction scheduling

Details Method for register allocation during instruction scheduling Method for register allocation during instruction scheduling

2003-12-12

2009-02-03

Patel, Niketa I. (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

C712S216000, C717S153000, C717S161000

Reexamination Certificate

active

07487336

ABSTRACT:
The present disclosure relates to the allocation of registers the scheduling of instructions, and, more specifically, to the classifying of operands and allocation of registers to local operands.

REFERENCES:
patent: 6427234 (2002-07-01), Chambers et al.
patent: 6651247 (2003-11-01), Srinivasan
patent: 7007272 (2006-02-01), Clarke
S. Pinter, “Register Allocation with Instruction Scheduling: a New Approach”, Dept. of Electrical Engineering, Israel Institute of Technology, Haifa, Israel,19 pages, Jun. 1993.
D. Bradlee et al., “Integrating Register Allocation and Instruction Scheduling for RISCs”, Dept. of Computer Science, Univ. of Washington, Seattle, Washington, 1991, 9 pages.
G. Chaitin, “Register Allocation & Spilling Via Graph Coloring”, IBM Research, Yorktown Heights, NY, 1982, 4 pages.
M. Poletto et al., “Linear Scan Register Alocation” ACM Trans. on Programming Languages and Systems, vol. 21, No. 5, Sep. 1999, pp. 895-913.
S. Freudenberger et al., “Phase Ordering of Register Allocation and Instruction Scheduling”, Presented at Code Generation—Concepts, Tools & Techniques, Jul. 1991, 10 pages.
F. Chow et al., “The Priority-Based Coloring Approach to Register Allocation”, ACM Trans. on Programming Languages and Systems, vol. 12, No. 4, Oct. 1990, pp. 501-536.

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