Memory device with programmable control for activation of...

Static information storage and retrieval – Read/write circuit – Differential sensing

Reexamination Certificate

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Details

C365S210140, C365S210120, C365S210150

Reexamination Certificate

active

07623400

ABSTRACT:
An embodiment of the invention relate to a memory device including a memory plane composed of memory cells located at the intersection of lines and columns, and a dummy path designed to output a signal to activate read amplifiers arranged at the bottom of the columns in the memory plane, said dummy path including dummy memory cells connected between two dummy bit lines means of selecting at least one dummy cell designed to discharge at least one of the dummy bit lines, and control means connected to the two dummy bit lines to generate said activation signal, characterized in that said device includes means of programming the number of selected cells to discharge at least said dummy bit line, to adjust the time at which said activation signal is output.

REFERENCES:
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patent: 6181626 (2001-01-01), Brown
patent: 6285604 (2001-09-01), Chang
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patent: 6996020 (2006-02-01), Yoshida
patent: 6999367 (2006-02-01), Yamagami
patent: 2002/0186579 (2002-12-01), Yokozeki
patent: 2003/0202412 (2003-10-01), Nii et al.
patent: 2004/0202035 (2004-10-01), Tsujimura et al.
patent: 2005/0286323 (2005-12-01), Ohtsuki et al.
patent: 000422939 (1991-04-01), None
patent: 02002260386 (2002-09-01), None
French Search Report, FR 0606122 Dec. 21, 2006.

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