Engineering strain in thick strained-SOI substrates

Details Engineering strain in thick strained-SOI substrates Engineering strain in thick strained-SOI substrates

2006-05-30

2008-12-23

Smith, Bradley K (Department: 2891)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ordering or disordering

C438S510000, C257SE21634

Reexamination Certificate

active

07468313

ABSTRACT:
A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer. The wafer's active layer is biaxially strained and has first and second regions. The second region is amorphized to alter its strain component(s). The wafer is annealed to re-crystallize the amorphous semiconductor. First and second types of transistors are fabricated in the first region and the second region respectively. Third and possibly fourth regions of the active layer may be processed to alter their strain characteristics. A sacrificial strain structure may be formed overlying the third region. The strain structure may be a compressive. When annealing the wafer with the strain structure in place, its strain characteristics may be mirrored in the third active layer region. The fourth active layer region may be amorphized in stripes that run parallel to a width direction of the transistor strain to produce uniaxial stress in the width direction.

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International Search Report and Written Opinion.

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