Integrated DRAM-NVRAM multi-level memory

Details Integrated DRAM-NVRAM multi-level memory Integrated DRAM-NVRAM multi-level memory

2006-03-03

2008-11-25

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050, C365S185260, C365S185030, C257S314000, C257S316000

Reexamination Certificate

active

07457159

ABSTRACT:
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.

REFERENCES:
patent: 4448400 (1984-05-01), Harari
patent: 4870470 (1989-09-01), Bass
patent: 5057448 (1991-10-01), Kuroda
patent: 5140552 (1992-08-01), Yamauchi et al.
patent: 5196722 (1993-03-01), Bergendahl et al.
patent: 5399516 (1995-03-01), Bergendahl et al.
patent: 5598367 (1997-01-01), Noble
patent: 5623442 (1997-04-01), Gotou et al.
patent: 5880991 (1999-03-01), Hsu et al.
patent: 5932908 (1999-08-01), Noble
patent: 5973344 (1999-10-01), Ma
patent: 6141248 (2000-10-01), Forbes
patent: 6166407 (2000-12-01), Ohta
patent: 6185712 (2001-02-01), Kirihata et al.
patent: 6232643 (2001-05-01), Forbes
patent: 6246606 (2001-06-01), Forbes
patent: 6266272 (2001-07-01), Kirihata
patent: 6282118 (2001-08-01), Lung
patent: 6297989 (2001-10-01), Cloud
patent: 6391755 (2002-05-01), Ma
patent: 6424011 (2002-07-01), Assaderaghi et al.
patent: 6452856 (2002-09-01), Forbes
patent: 6498739 (2002-12-01), Cloud et al.
patent: 6503794 (2003-01-01), Watanabe et al.
patent: 6531731 (2003-03-01), Jones, Jr. et al.
patent: 6541815 (2003-04-01), Mandelman et al.
patent: 6617651 (2003-09-01), Ohsawa
patent: 6661042 (2003-12-01), Hsu
patent: 6717205 (2004-04-01), Gratz
patent: 6741519 (2004-05-01), Forbes
patent: 6743681 (2004-06-01), Bhattacharyya
patent: 6771538 (2004-08-01), Shukuri
patent: 6784480 (2004-08-01), Bhattacharyya
patent: 6785167 (2004-08-01), Kurth
patent: 6790727 (2004-09-01), Jones, Jr. et al.
patent: 6791877 (2004-09-01), Miura
patent: 6798008 (2004-09-01), Choi
patent: 6801994 (2004-10-01), Beckert et al.
patent: 6878991 (2005-04-01), Forbes
patent: 6979857 (2005-12-01), Forbes
patent: 7148538 (2006-12-01), Forbes
patent: 7157771 (2007-01-01), Forbes
patent: 7158410 (2007-01-01), Bhattacharyya et al.
patent: 7190616 (2007-03-01), Forbes et al.
patent: 7241654 (2007-07-01), Forbes
patent: 7273784 (2007-09-01), Bhattacharyya
patent: 2004/0041208 (2004-03-01), Bhattacharyya
patent: 2004/0042256 (2004-03-01), Forbes
patent: 1 383 134 (2004-01-01), None
patent: 402240960 (1990-09-01), None
patent: 410289980 (1998-10-01), None
S. Okhonin, et al “A SOI Capacitor-less IT-DRAM Concept”, 2001 IEEE International SOI Conference, Oct. 2001, pp. 153-154.
P. Fazan, et al “Capacitor-Less 1-Transistor DRAM”, 2002 IEEE International SOI Conference, Oct. 2002, pp. 10-13.
P. Fazan, et al “A Simple Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs”, IEEE 2002 Custom Integrated Circuits Conference, pp. 99-102.
T. Ohsawa, et al. “Memory Design Using One-Transistor Gain Cell on SOI”, IEEE International Solid State Circuit Conference, 2002, pp. 152-153, 454.
T. Ohsawa, et al. “A Memory Using One-Transistor Gain Cell on SOI (FBC) with Performance Suitable for Embedded DRAMS”, 2003 Symposium on VLSI Circuits, Digest of Technical Papers, Jun. 12-14, 2003, pp. 93-96.
T. Ohsawa, et al. “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.
A. Battacharyya, et al. “Physical and Electrical Characteristics of LPCVD Silicon Rich Nitride”, ECS Tech Digest, New Orleans, Louisiana, vol. 84-2, Oct. 11, 1984, pp. 1-19.

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