Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-03-29

2008-12-02

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S201000

Reexamination Certificate

active

07460426

ABSTRACT:
Through setting an internal test mode, a refresh operation for a DRAM is carried out by externally inputted address signals, instead of internally generated address signals, while maintaining the same number of memory cell arrays to be activated as that of memory cell arrays which are concurrently activated in a refresh for memory cell arrays. This configuration needs no drastic addition of circuits and allows a reduction in disturb test time for a plurality of memory cell arrays.

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