Circuit including a deskew circuit for asymmetrically...

Details Circuit including a deskew circuit for asymmetrically... Circuit including a deskew circuit for asymmetrically...

2005-04-21

2008-12-23

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C365S194000

Reexamination Certificate

active

07469354

ABSTRACT:
A circuit including a deskew circuit. The deskew circuit is configured to receive a first signal having a first edge delayed from a second edge of a second signal by a first delay and a third edge delayed from a fourth edge of the second signal by a second delay. The deskew circuit is configured to provide a third signal having a first deskewed edge delayed from the first edge by a third delay and a second deskewed edge delayed from the third edge by a fourth delay. The difference between the fourth delay and the third delay is substantially equal to the difference between the first delay and the second delay.

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