Semiconductor assembly for improved device warpage and...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Die bond

Reexamination Certificate

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Details

C257S777000, C257SE27137, C257SE21122, C257SE21480, C257SE21519, C438S106000, C438S107000, C438S455000, C438S457000

Reexamination Certificate

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07462943

ABSTRACT:
A semiconductor device with a chip (505), its position defining a plane, and an insulating substrate (503) with first and second surfaces; the substrate is substantially coplanar with the chip, without warpage. One of the chip sides is attached to the first substrate surface using adhesive material (504), which has a thickness. The thickness of the adhesive material is distributed so that the thickness (504b) under the central chip area is equal to or smaller than the material thickness (504a) under the peripheral chip areas. Encapsulation compound (701) is embedding all remaining chip sides and the portions of the first substrate surface, which are not involved in the chip attachment. When reflow elements (720) are attached to the substrate contact pads, they are substantially coplanar with the chip.

REFERENCES:
patent: 5252850 (1993-10-01), Schempp
patent: 5509464 (1996-04-01), Turner
patent: 6392143 (2002-05-01), Koshio
patent: 6446948 (2002-09-01), Allen
patent: 7148081 (2006-12-01), Higashino et al.
patent: 2001/0005602 (2001-06-01), Mimata et al.
patent: 2002/0090759 (2002-07-01), Hashimoto
patent: 2003/0052419 (2003-03-01), Ujiie et al.
patent: 2003/0170444 (2003-09-01), Stewart et al.

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