Multi-port memory device

Details Multi-port memory device Multi-port memory device

2006-09-27

2008-11-04

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Read/write circuit

Parallel read/write

C365S189050, C365S196000, C365S230030, C365S230050, C365S230060

Reexamination Certificate

active

07447095

ABSTRACT:
A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port memory device includes: a write clock generating unit for generating a write clock selectively toggled only while write data are applied; a write control unit for generating a write flag signal group and a write driver enable signal in response to the write clock and a write command; a data latch unit for outputting intermediate write data by storing burst write data under the control of the write flag signal group; and a write driver for receiving the intermediate write data to write final write data in a memory cell of a corresponding bank in response to the write driver enable signal and a data mask signal group.

REFERENCES:
patent: 2007/0070743 (2007-03-01), Do et al.
patent: 2007/0070778 (2007-03-01), Do
patent: 1020000053662 (2000-08-01), None

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