Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2006-02-28
2008-11-25
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C709S203000, C710S052000, C710S306000, C711S133000, C711S154000
Reexamination Certificate
active
07457901
ABSTRACT:
A microprocessor including processor logic and sparse write logic which asserts address signals and request signals to provide an address and a request for a cache line memory write transaction, which provides one of multiple sparse memory write transactions on the request signals and which provides corresponding enable bits on the address signals. Each sparse memory write transaction corresponds with one of multiple granularities of data. For example, if the sparse memory write transaction is a quad-pumped cache line write for eight quadwords, the enable bits may be a selected one of byte, word, doubleword, quadword, doublequadword, etc., enable bits. A method of performing a sparse write transaction including providing an address and a request for a memory write transaction, indicating that the memory write transaction is a selected sparse write transaction, asserting enable signals for the selected sparse write transaction, and providing data for the sparse write transaction.
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Daley Christopher A
Dang Khanh
Huffman James W.
Huffman Richard K.
Stanford Gary R.
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