System and method for managing table lookaside buffer...

Details System and method for managing table lookaside buffer... System and method for managing table lookaside buffer...

2006-09-22

2008-12-30

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S207000

Reexamination Certificate

active

07472253

ABSTRACT:
A computer system comprising a main memory and a processor die coupled to the main memory by a first bus. The processor die includes a processor core coupled to a first cache memory and multiple base and bounds registers (BBRS). Each of BBRs have a base virtual address field, an ending virtual address field and a base physical address field. The first cache memory has a table lookaside buffer (TLB) entry stored therein.

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