Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2006-12-18
2008-11-18
Pham, Ly D (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185240, C365S185280, C365S185300, C365S185330
Reexamination Certificate
active
07453736
ABSTRACT:
An electrically erasable charge trap nonvolatile memory cell has an initial threshold voltage, a program voltage that is higher than the initial threshold voltage, and an erase threshold voltage that is lower than the program threshold voltage but is higher than the initial threshold voltage. The programmed electrically erasable charge trap nonvolatile memory cells may be erased by applying an erase voltage for a time interval that is sufficient to lower the threshold voltage the transistor from a program threshold voltage to an erase threshold voltage that is lower than the program threshold voltage, but is higher than the initial threshold voltage. The time interval may be determined by repeatedly performing an endurance test using a time interval that is increased or decreased from an initial time interval, to obtain the time interval that meets an endurance specification, or allows a read to be performed successfully.
REFERENCES:
patent: 5099297 (1992-03-01), Hazani
patent: 5132935 (1992-07-01), Ashmore, Jr.
patent: 5396459 (1995-03-01), Arakawa
patent: 5400286 (1995-03-01), Chu et al.
patent: 5537358 (1996-07-01), Fong
patent: 5600593 (1997-02-01), Fong
patent: 5648930 (1997-07-01), Randazzo
patent: 5694357 (1997-12-01), Mori
patent: 5699298 (1997-12-01), Shiau et al.
patent: 5790460 (1998-08-01), Chen et al.
patent: 5815445 (1998-09-01), Hull et al.
patent: 5886905 (1999-03-01), Yokozawa
patent: RE36210 (1999-05-01), Santin
patent: 5923589 (1999-07-01), Kaida et al.
patent: 5999444 (1999-12-01), Fujiwara et al.
patent: 6026026 (2000-02-01), Chan et al.
patent: 6054732 (2000-04-01), Ho et al.
patent: 6108263 (2000-08-01), Bauser et al.
patent: 6134141 (2000-10-01), Wong
patent: 6160739 (2000-12-01), Wong
patent: 6160740 (2000-12-01), Cleveland
patent: 6169693 (2001-01-01), Chan et al.
patent: 6188609 (2001-02-01), Sunkavalli et al.
patent: 6222768 (2001-04-01), Hollmer et al.
patent: 6243298 (2001-06-01), Lee et al.
patent: 6261884 (2001-07-01), Ho et al.
patent: 6266281 (2001-07-01), Derhacobian et al.
patent: 6347053 (2002-02-01), Kim et al.
patent: 6418062 (2002-07-01), Hayashi et al.
patent: 6442075 (2002-08-01), Hirano
patent: 6483752 (2002-11-01), Hirano
patent: 6490205 (2002-12-01), Wang et al.
patent: 6504762 (2003-01-01), Harari
patent: 6552387 (2003-04-01), Eitan
patent: 6687648 (2004-02-01), Kumar et al.
patent: 6754109 (2004-06-01), Fastow et al.
patent: 6829175 (2004-12-01), Tsai et al.
patent: 2001/0004325 (2001-06-01), Choi
patent: 2001/0043492 (2001-11-01), Lee et al.
patent: 2002/0057599 (2002-05-01), Miyawaki et al.
patent: 2002/0141237 (2002-10-01), Goda et al.
patent: 2003/0076710 (2003-04-01), Sofer et al.
patent: 2003/0179630 (2003-09-01), Choi
patent: 2003/0185056 (2003-10-01), Yoshida et al.
patent: 2005/0111257 (2005-05-01), Eitan
patent: 10-0244861 (1999-11-01), None
Sharma,Semiconductor Memories: Technology, Testing, and Reliability, IEEE Press, 1997, pp. 104-116.
Myers Bigel Sibley & Sajovec P.A.
Pham Ly D
Samsung Electronics Co,. Ltd.
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