Phase detector and method for a shortening...

Details Phase detector and method for a shortening... Phase detector and method for a shortening...

2003-02-21

2008-12-30

Tran, Khai (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S312000

Reexamination Certificate

active

07471756

ABSTRACT:
In a phase-locked loop (PLL), a phase detector receives a reference signal and a feedback oscillator signal, generates a phase-detect pulse having a first duration in response to one of the reference and feedback signals, and generates a phase-correction pulse having second, shorter duration in response to the phase-detect pulse. By shortening the phase-correction pulse, such a phase detector can reduce or eliminate the overcorrection period during which the phase-correction pulse is active after phase correction is achieved, and thus can reduce or eliminate the phase error that the overcorrection period may introduce into a PLL's oscillator signal.

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Kurt M. Ware, et al., “A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors”, IEEE Journal of Solid-State Circuits, vol. 24, No. 6, Dec. 1989, pp. 1560-1568.

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