Method and device for supporting verification, and computer...

Details Method and device for supporting verification, and computer... Method and device for supporting verification, and computer...

2006-09-14

2008-12-23

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07469393

ABSTRACT:
In a verification support device, a logical expression expressing an operation of a pattern generator can be acquired. The pattern generator includes a basic pattern generator, priority pattern generators, priority pattern selection conditions, and selector circuits. The selector circuits connect the basic pattern generator, the priority pattern generators, and the priority pattern selection conditions. Output of the basic pattern generator and outputs of the priority pattern generators are respectively connected to a signal input of a corresponding selector circuit. Outputs of the priority pattern selection conditions are connected to an ON/OFF control input of each selector circuit. An n-th selector circuit, among all selector circuits, is connected to an input terminal of a verification subject.

REFERENCES:
patent: 2002/0138812 (2002-09-01), Johannsen
Jun Yuan et al.; “Constraint Synthesis for Environment Modeling in Functional Verification”; Design Automation Conference 2003; pp. 296-299.

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