Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-05-04
2008-11-11
Abraham, Esaw (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S786000
Reexamination Certificate
active
07451376
ABSTRACT:
In one embodiment, bit processing units are provided for the 1stto Mthrows (M=p1×m1) of a parity-check matrix that includes a first parity-check matrix and second parity-check matrix adjacent thereto. The first and second parity-check matrices include (n1×m1) and (n2×m2) permuted matrices, respectively. The bit processing units sequentially update bit information corresponding to column positions included in the respective rows of the first and second parity-check matrices, a bit at each of the column positions being set to “1”. Parity processing units update parity information corresponding to row positions in p1columns of each of the n1column blocks of the first parity-check matrix, and corresponding to row positions in p2columns of each of the n2column blocks of the second parity-check matrix, a bit at each of the row positions being set to “1”.
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Abraham Esaw
Kabushiki Kaisha Toshiba
Pillsbury Winthrop Shaw & Pittman LLP
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