Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Having heterojunction
Reexamination Certificate
2006-12-04
2008-12-09
Nguyen, Dao H (Department: 2818)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Having heterojunction
C438S319000, C438S322000, C438S335000, C257S522000, C257S565000, C257SE21573, C257SE21581
Reexamination Certificate
active
07462547
ABSTRACT:
A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.
REFERENCES:
patent: 5128271 (1992-07-01), Bronner et al.
patent: 5494836 (1996-02-01), Imai
patent: 5506427 (1996-04-01), Imai
patent: 5798561 (1998-08-01), Sato
patent: 5930635 (1999-07-01), Bashir et al.
patent: 5962880 (1999-10-01), Oda et al.
patent: 6346453 (2002-02-01), Kovacic et al.
patent: 6492238 (2002-12-01), Ahlgren et al.
patent: 6777302 (2004-08-01), Chen et al.
patent: 6940149 (2005-09-01), Divakaruni et al.
patent: 6964907 (2005-11-01), Hopper et al.
patent: 7022578 (2006-04-01), Verma et al.
patent: 2003/0057458 (2003-03-01), Freeman et al.
patent: 2003/0098465 (2003-05-01), Suzumura et al.
patent: 2003/0109109 (2003-06-01), Freeman et al.
Akatsu Hiroyuki
Divakaruni Rama
Khater Marwan
Schnabel Christopher M.
Tonti William
International Business Machines - Corporation
Neff Daryl
Nguyen Dao H
Schnurmann H. Daniel
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