Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-14
2008-12-30
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07472360
ABSTRACT:
A method is provided for implementing enhanced wiring capability for electronic laminate packages. Electronic package physical design data are received. Instances of line width and space limit violations in the electronic package physical design data are identified. The identified instances of line width and space limit violations are evaluated using predefined qualified options and tolerance limitations and the electronic package physical design data are modified to optimize shapes to replace the instances of line width and space limit violations.
REFERENCES:
patent: 6184581 (2001-02-01), Cornell et al.
patent: 6534872 (2003-03-01), Freda et al.
patent: 2007/0124709 (2007-05-01), Li et al.
Bartley Gerald Keith
Becker Darryl John
Dahlen Paul Eric
Germann Philip Raymond
Maki Andrew Benson
Chiang Jack
International Business Machines - Corporation
Memula Suresh
Pennington Joan
LandOfFree
Method for implementing enhanced wiring capability for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for implementing enhanced wiring capability for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for implementing enhanced wiring capability for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4033577