Dual-gate semiconductor devices with enhanced scalability

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S366000, C257S576000, C438S211000

Reexamination Certificate

active

07459755

ABSTRACT:
A scalable semiconductor device is formed using control gates formed on opposite sides of a semiconductor layer. A first control gate is formed electrically isolated from a first surface of the semiconductor layer by a first dielectric layer, such that, when a first voltage is applied on the first control gate, a first depletion region is formed in the semiconductor layer opposite the first control gate. A second control gate and a third control gate are also formed, each isolated from the semiconductor region by a second dielectric layer formed on a second surface of the semiconductor layer opposite the first surface. The second and the third control gates are offset from the first control gate such that, when a second voltage is applied to the second and third control gates, depletion regions are formed opposite the second and third control gates, respectively, such that each of the depletion regions opposite the second and third control gates overlaps the first depletion region to serve as source and drain regions, when filled with mobile carriers, of a field-effect transistor to the first depletion region, which serves as a channel region of the field-effect transistor.

REFERENCES:
patent: 5124769 (1992-06-01), Tanaka et al.
patent: 2003/0075755 (2003-04-01), Yamazaki

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