Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-22
2008-11-18
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07454731
ABSTRACT:
Static timing and/or noise analysis are performed on a netlist of an integrated circuit, to estimate behavior of the netlist and to identify at least one violation by said behavior of a corresponding requirement thereon, such as setup time, hold time or bump height in a quiescent net. Thereafter, effect of engineering change order (ECO) to correct the violation are automatically analyzed, based on the layout, the parasitics, the timing and/or noise behavior, and the violation, followed by generation of a constraint on the behavior (called “ECO” constraint), such as a timing constraint and/or a noise constraint. Next, the ECO constraint is automatically used, e.g. in a place and route tool, to select an ECO repair technique, from several ECO repair techniques that can overcome the violation. The selected ECO repair technique is automatically applied to the layout, to generate a modified layout which does not have the violation.
REFERENCES:
patent: 7069528 (2006-06-01), Kovacs et al.
patent: 7363605 (2008-04-01), Kondratyev et al.
patent: 7363607 (2008-04-01), Birch et al.
patent: 7383522 (2008-06-01), Murgai et al.
Elmore, W.C. “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers”, Journal of Applied Physics, vol. 19, Jan. 1948, pp. 55-63.
Hanchate, Narender et al., “A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise”, Proceedings of the 19th International Conference on VLSI Design, (VLSID'06), 2006, 283-290, 8 pgs.
Alpert, Charles J. et al., “Buffer Insertion for Noise and Delay Optimization”, IEEE Transactions on computer-aided design of integrated circuits and systems, Nov. 1999, 1633-1645, vol. 18, No. 11, 13 pgs.
Jiang, Iris Hui-Ru et al., “Crosstalk-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing”, IEEE Transactions on computer-aided design of integrated circuits and systems, Sep. 2000, 999-1010, vol. 19, No. 9, 12 pgs.
Vittal, Ashok et al., “Crosstalk Reduction for VLSI”, IEEE Transactions on computer-aided design of integrated circuits and systems, Mar. 1997, 290-298, vol. 16, No. 3, 9 pgs.
Saxena, Prashant et al., “A Postprocessing Algorithm for Crosstalk-Driven Wire Perturbation”, IEEE Transactions on computer-aided design of integrated circuits and systems, Jun. 2000, 691-102, vol. 19, No. 6, 12 pgs.
Becer, Murat R. et al., “Postroute Gate Sizing for Crosstalk Noise Reduction”, IEEE Transactions on computer-aided design of integrated circuits and systems, Dec. 2004, 1670-1677, vol. 23, No. 12, 8 pgs.
Odabasioglu, Altan et al., “PRIMA: Passive Reduced-Order Interconnect Macromodeling Algorithm”, IEEE Transactions on computer-aided design of integrated circuits and systems, Aug. 1998, 645-654, vol. 17, No. 8, 10 pgs.
Zhou, Hai et al., “Global Routing with Crosstalk Constrains”, IEEE Transactions on computer-aided design of integrated circuits and systems, Nov. 1999, 1683-1688, vol. 18, No. 11, 6 pgs.
Xiao, Tong et al., “Gate Sizing to Eliminate Crosstalk Induced Timing Violation”, Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors (ICCD'01), 2001, 186-191, 6 pgs.
Chen, Chung-Ping et al., “Noise-aware Repeater Insertion and Wire Sizing for On-chip Interconnect Using Hierarchical Moment-Matching”, 36thAnnual Conference on Design Automation (DAC'99), 1999, 502-506, 5 pgs.
Bai, Xiaoliang et al., “Noise-Aware Driver Modeling for Nanometer Technology”, Fourth International Symposium on Quality Electronic Design, 2003, 6 pgs.
Shepard, Kenneth L., “Design Methodologies for Noise in Digital Integrated Circuits”, 35thDesign Automation Conference, 1998, 6 pgs.
Shepard, Kenneth L. et al., “Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits”, IEEE Transactions on computer-aided design of integrated circuits and systems, Aug. 1999, 1132-1150, vol. 18, No. 8, 19 pgs.
Guardiani, C. et al., “Modeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting”, Proc. of PATMOS, Oct. 1998, 287-296, (Advanced Research, Central R&D, DAIS, STMicroelectronics, via C. Olivetti, 2, I-20041 Agrate B., (MI), Italy), 10pgs.
Pandini, Davide et al., “Network Reduction for Crosstalk Analysis in Deep Submicron Technologies”, International Workshop on Timing Issues, 1997, (Advanced Research, SGS-THOMSON Microelectronics, via C. Olivetti 2, 20041 Agrate Brianza, Italy), 10 pgs.
Fallah-Tehrani Peivand
Kasnavi Alireza
Oh Nahmsuk
Chiang Jack
Silicon Valley Patent & Group LLP
Suryadevara Okmar
Synopsys Inc.
Tat Binh C
LandOfFree
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