Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-11-16
2008-12-09
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07464320
ABSTRACT:
A semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged and operates in sync with a clock signal. A read and write operations are performed in the same cycle of the clock signal. The read operation allows the read column selection lines that have been designated by a first column address to connect the read data bus to the bit lines. The write operation allows the write column selection lines that have been designated by a second column address to connect the write data bus to the bit lines. Further, in the write operation, the data obtained by combining the data that has been error-corrected by the syndrome generation circuit and correction circuit with the data that has been input to the input circuit is coded by the code generation circuit and written in the memory cells.
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Yasuhiro Takai, et al., “250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture”, IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, pp. 426-431.
Miyano Shinji
Nagai Takeshi
Chase Shelly A
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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