Circuit for generating a cyclic code

Details Circuit for generating a cyclic code Circuit for generating a cyclic code

2005-07-07

2008-12-23

Abraham, Esaw (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S758000, C714S786000

Reexamination Certificate

active

07469374

ABSTRACT:
A cyclic code is generated by a circuit including a group of logic gates that generate one multiple-bit code segment from another multiple-bit code segment. The logic gates receive B initial bits, where B is the degree of the generator polynomial, and generate one complete (2B−1)-bit code cycle, from which a clocked address generator and a barrel shifter select successive C-bit segments for output (C>1). This arrangement outputs C bits of code per clock pulse and therefore does not require a special high-frequency clock signal.

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