Impedance adjustment circuit and integrated circuit device

Details Impedance adjustment circuit and integrated circuit device Impedance adjustment circuit and integrated circuit device

2006-03-23

2008-10-28

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S030000

Reexamination Certificate

active

07443203

ABSTRACT:
An NMOS impedance adjustment circuit has a comparator circuit for comparing with a reference electric potential VREFn a divided voltage potential Vin produced by an NMOS array and an external reference resistance. The NMOS array simulates the impedance of an output buffer circuit on the basis of the comparison result. The comparator circuit has three differential circuits. Three 2-input NAND gates and a single three-input NAND gate take the majority of output values of the differential circuits and output the result from the comparator circuit. A reduction of impedance adjustment precision caused by variability within the chip can thereby be inhibited.

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patent: 2005-26890 (2005-01-01), None

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