Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2005-03-14
2008-10-28
Peikari, B. James (Department: 2189)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S001000, C711S200000
Reexamination Certificate
active
07444458
ABSTRACT:
A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.
REFERENCES:
patent: 4293910 (1981-10-01), Flusche et al.
patent: 4373181 (1983-02-01), Chisholm et al.
patent: 4730251 (1988-03-01), Aakre et al.
patent: 5029209 (1991-07-01), Strong, Jr. et al.
patent: 5293498 (1994-03-01), Iwatsubo
patent: 5412788 (1995-05-01), Collins et al.
patent: 5430859 (1995-07-01), Norman et al.
patent: 5551053 (1996-08-01), Nadolski et al.
patent: 5590374 (1996-12-01), Shariff et al.
patent: 5617537 (1997-04-01), Yamada et al.
patent: 5627784 (1997-05-01), Roohparvar
patent: 5636342 (1997-06-01), Jeffries
patent: 5640332 (1997-06-01), Baker et al.
patent: 5640594 (1997-06-01), Gibson et al.
patent: 5687117 (1997-11-01), Chevallier et al.
patent: 5790782 (1998-08-01), Martinez et al.
patent: 5873123 (1999-02-01), Patel et al.
patent: 6175891 (2001-01-01), Norman et al.
patent: 6965923 (2005-11-01), Norman et al.
“Draft Standard for A High-Speed Memory Interface (SyncLink)”,Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, New York: Institute of Electrical and Electronics Engineers, Inc., (1996), 1-52.
Lakhani Vinod C.
Norman Robert D.
Micro)n Technology, Inc.
Peikari B. James
Schwegman Lundberg & Woessner, P.A.
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