Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-07
2008-08-26
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S098000, C700S110000, C700S120000, C700S121000, C430S005000, C378S035000
Reexamination Certificate
active
07418694
ABSTRACT:
A method for generating test patterns utilized in manufacturing a semiconductor device includes creating mini-data concerning a partial area pattern used in designing the semiconductor device, subjecting the mini-data to data processing in accordance with a condition of a manufacturing process of the semiconductor device, thereby creating processed mini-data, extracting a marginless point in the processed mini-data where a process margin is less than a predetermined threshold in a manufacturing process of the semiconductor device, determining a class of the marginless point in accordance with a criticality and a category of the marginless point, determining a parameter and a range of the parameter used for the marginless point in accordance with the class of the marginless point, and generating a plurality of test patterns to which different values of the parameter are respectively applied within the range.
REFERENCES:
patent: 5286656 (1994-02-01), Keown et al.
patent: 6902855 (2005-06-01), Peterson et al.
patent: 6952818 (2005-10-01), Ikeuchi
patent: 2006/0236294 (2006-10-01), Saidin et al.
patent: 2007/0032896 (2007-02-01), Ye et al.
patent: 2004-294551 (2004-10-01), None
Qian et al., “Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis”, Proceedings of Fourth International Symposium on Quality Electronic Design, Mar. 24-26, 2003, pp. 125-130.
Miwa et al., “A New Method for Calculating One-Dimensional Process Margin in Consideration of Process Variations”, 1999 4th International Workshop on Statistical Metrology, 1999, pp. 58-61.
Inoue et al., “Level-Specific Strategy of KrF Microlithography for 130 nm DRAMs”, International Electron Devices Meeting, Dec. 5-8, 1999, pp. 809-812.
Kobayashi et al., “Mask Manufacturing System, Mask Data Creating Method and Manufacturing Method of Semiconductor Device”, U.S. Appl. No. 11/440,086, filed May 25, 2006.
Ikeuchi Atsuhiko
Kobayashi Sachiko
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Kik Phallaka
LandOfFree
Method for generating test patterns utilized in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for generating test patterns utilized in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for generating test patterns utilized in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4014555