Method for detecting flaws in a functional verification plan

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000

Reexamination Certificate

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07434184

ABSTRACT:
This method uses 2 copies of the design under test. These 2 copies use different values (including primary inputs and initial states) to feed the supposedly irrelevant logic while using the same (or consistent as desired) values to feed the feature being verified. Symbolic method is used to efficiently determine whether the feature being verified behaves identically (or consistently as expected) in the 2 copies for all possible cases in the supposedly irrelevant logic.

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